1. Field of the Invention
The invention relates generally to a circuit for the detection of a start condition, a circuit for the detection of a stop condition, and a data-detection circuit to detect data sent on a bus according to the IIC protocol.
The IIC (Inter-Integrated Circuit) bus and the associated IIC protocol were developed in the 1980s to make it easy to connect electronic systems together. Initially designed for home equipment, they have now become a preferred means of configuring complex electronic components.
The IIC protocol can be used to set up communication between a very wide variety of electronic components by means of a bus that conveys only three signals: a data signal SDA containing data and/or addresses to be transmitted, a clock signal SCL setting the rate of the signal SDA, and an electrical reference (ground) signal.
This makes it possible to obtain equipment with very powerful functions (provided with all the power of microprogrammed systems) while keeping a printed circuit board that is very simple as compared with one having a classic circuit diagram.
Today, the IIC protocol has become a standard and there are many varied electronic components capable of communicating by means of this protocol: they include microprocessors, memories, boards etc.
The IIC protocol defines the succession of possible logic states on the signals SDA and SCL associated with an IIC bus connecting at least two components that have to communicate.
Each component connected to the bus constantly monitors the signals SDA and SCL, especially in order to know if the bus is free, if the data transmitted on the bus is intended for it (in the case of the slave component), or if the data that it transmits is accurately transmitted (in the case of the master component).
To take control of the bus in order to transmit data, the bus must initially be at rest. This corresponds to the state where the signals SDA and SCL are equal to “1”.
After it has been verified that the bus is free, a component may take control of the bus; this component then becomes the master and imposes the clock signal SCL. It can then transmit data to one or more slave components.
To transmit one byte of data on the free bus, the master transmits a start condition message on the signal SDA. This start condition message indicates that the data will be transmitted. It is followed by a data byte to be transmitted and an enabling bit (where SDA is equal to 1). During this phase, a leading edge of the clock signal SCL enables each bit sent on the signal SDA. The slave (the addressee of the transmitted byte) then imposes a “0” on the signal SDA, thus, informing the master that it has accurately received the transmitted byte. Finally, the master transmits a stop condition signal on the signal SDA, to indicate that the bus will be released.
The start condition is fulfilled when the following conditions occur: with the signals SDA and SCL initially at “1” (bus idle, instant t1 in FIGS. 6a, 6b), the signal SDA goes to 0” (instant t2) while the signal SCL remains at “1” for at least a time TDLC after the trailing edge of the signal SDA (instant t3). If necessary, a minimum time TCHDX may be required between the last leading edge of SCL (instant t1) and the trailing edge of SDA (instant t2) to ensure that the bus is available.
The stop condition is fulfilled when the following conditions occur: with the signal SDA initially at “0” and the signal SCL initially at “1” (instant t4), the signal SDA goes to “1” (instant t5) while the signal SCL remains at “1”. As the case may be, a minimum time TCHDH may be required between the leading edge of SCL (instant t4) and the leading edge of SDA (instant t5).
2. Description of the Prior Art
To monitor the signals SDA and SCL on the bus, the electronic components connected to the bus typically have a circuit for the detection of a start condition and/or a stop condition.
In a known way, detection circuits of this kind are made according to known analog schemes using resistors and capacitors. Specifically, they use delay circuits, based on inverters, capacitors and resistors, to measure the time between the leading edges and/or trailing edges of the signals SDA and SCL.
The resistors and capacitors have many drawbacks. These elements are large-sized in terms of silicon surface area occupied. Their resistance and/or their capacitance can change from one element to another, as a result of the process used to make them. Their resistance and/or their capacitance are furthermore imprecise and liable to drift in time, depending especially on the conditions of use.
Naturally, the drawbacks of the data detectors are the same as those of the resistors and capacitors that form them.
Therefore, a need has arisen for a detector that overcomes these problems of size and precision.